RFIC (Radio Frequency Integrated Circuit) design is a highly complex and challenging field that involves multiple technical disciplines, including but not limited to microwave engineering, electromagnetics, circuit design and simulations. Therefore, interdisciplinary knowledge is required to achieve high-quality RFIC design and eventually lead to high-performance RFIC chips.

RFIC Design normally includes a series of IP (Intellectual Property) circuits, such as:

• Power Amplifiers, PA
• Low Noise Amplifiers, LNA
• Voltage-Controlled Oscillators, VCO

These RF IP circuits encompass not only active components but also a significant number of passive components, such as:

• Inductor
• Transformer
• Matching Network

These passive components play a crucial role in RFIC design, often used for the conversion of single-ended signals and differential signals, and matching input or output impedances. Traditional RFIC Design requires precise design and optimization of both active and passive partitions, and it is not only a time-consuming iterative process, but also heavily depends on particular designers' experience.

Targeted at RF chip design, RFIC-GPT from IC Prophet utilizes AI algorithms to calculate and generate schematics or GDSII layouts of RF devices and circuits that meet designers' specifications(e.g. Q-factor, inductance, coupling coefficient of transformers, gain of Power Amplifiers, etc.). With an accuracy of at least 95%, designers can directly apply the generated results in their design. RFIC-GPT is capable of assisting RF designers in expeditiously finding optimal design parameters, substantially reducing the tedious and iterative manual searching process. RFIC-GPT has already been silicon-proven and commercial chips enabled by RFIC-GPT are shipping.

Currently support：

• Passive devices/circuits: Inductor, Transformer, Matching Network, Multi-value Matching Network
• Active circuits: PA Active Circuit

RFIC-GPT simplifies and accelerates the complex RF design process. Users only need to input design specifications, and within seconds the GDSII or schematics will be generated. The results can be downloaded and applied in standard design platforms such as Cadence Virtuoso, Keysight ADS, etc.

RFIC-GPT Online version: www.RFIC-GPT.com

The offline version is RFIC-GPT Pro, which offers a broader spectrum of application scenarios, with more complete functions and customized services. For inquiries, please email: sales@icprophet.com.

You can get the design of RF circuits and GDSII files from RFIC-GPT within 3 steps.

Step 1: Enter Design Specifications

Select passive devices or active circuits on the leftside navigation bar, and enter your design specifications.

Step 2: Click “Calculate” and view the calculated results. Each of the calculated results is optimized towards certain specifications.

Step 3: Select the most suitable result for your design, and click “Download GDSII layout”. You can either:

• Import the GDSII directly into your Cadence Virtuoso

or

• Check the generation code in the downloaded .txt file, and enter it into RFIC-Generator .

Demonstration Video

https://icprophet-wwwweb.oss-cn-shanghai.aliyuncs.com/wwwweb/video/helpvide5.mp4

• Design Frequency (GHz)

input range: 0.5GHz ~ 85GHz

Design frequency refers to the operating frequency of the inductor in a specific circuit. For now, RFIC-GPT supports a range between 0.5GHz and 85GHz.

• Quality Factor Q

input range: 2 ~ 50

Quality factor Q is one of the most important specifications of an inductor. It indicates an inductor's performance at the operating frequency. Generally, the higher the Q, the lower the loss, and the better the performance. Inductors with high Q are more efficient in signal transmission circuits and filter circuits.

Tips for setting the Q: Generally, setting the Q to around 10 would suffice for most on-chip inductor scenarios. If the required Q is unclear, we suggest you to set the inductance $L$ first, then adjust the Q upwards from 10. Observe how high the Q can go while satisfying the required $L$. Note that the technology node and layer thickness should be chosen too.

• Inductance L (pH)

input range：40pH-10000pH (Exception: the upper boundary is raised to 25000pH for 130nm node)

The inductance is measured in picohenries(pH). Choosing the correct inductance is crucial for ensuring impedance matching and efficient signal transmission. The inductance here can be regarded as a summation of both the inductive and capacitive properties of the inductor coil. For an inductor with an impedance of $Z$, its inductance $L$ is calculated as follow:

$$L=\frac{imag(Z)}{\omega}, \omega=2\pi\times freq $$

• Self Resonant Frequency SRF (>GHz) (optional)

The SRF of an inductor is the frequency at which the parasitic capacitance of the inductor resonates with the ideal inductance of the inductor, resulting in an extremely high impedance. The inductance only acts like an inductor below its SRF. Therefore, SRF is usually greater than 1.5 times of the operating frequency as a matter of concern in stability and reliability.

The default input value for SRF is 1.5 times the Design Frequency.

• Technology Node

At present, the technology nodes we support include 22nm, 28nm, 40nm, 55nm, 65nm, 110nm and 130nm.

• Metal Layer Thickness (µm)

You should choose the metal layer thickness in accordance with your design and the corresponding technology files.

Different metal layers have varying thicknesses and dielectric properties, and the electrical performance of inductor coils is primarily related to the thickness of the metal layer. Please refer to the techfile or the .PROC file of the PDK and check the data.

Tips for setting the metal layer thickness: The accuracy of the results improves as the chosen metal layer thickness closely matches the thickness of the metal layer you used in your design.

• Signal Input Type

Signal Input Type refers to whether the signal is input into the inductor as a differential(DIFF) or single-ended(SINGLE) signal. Differential signal transmission is commonly used in high-speed data transmission or cases requiring better interference resistance. In contrast, single-ended signal transmission is typically used in general circuits but is more susceptible to electromagnetic interference. Choosing the appropriate signal input type (DIFF or SINGLE) is crucial for circuits' performance and stability.

• Max Layout Length (µm) & Max Layout Width (optional)

Max Layout Length/Width refers to the length and width constraints of the generated layout. Fill in the blanks according to your design requirements. You can also leave these blank. Generally, the larger the area, the more turns of the coil can be wound, resulting in a higher inductance value.

Fill in the “Inductor Specifications” according to your design. Click “Calculate” and you will get three sets of results, each of which has a different focus point:

1. optimized towards Q;
2. optimized towards $L$;
3. optimized towards all specifications and error-balanced.

The corresponding GDSII files are provided as well.

• If the calculated results meet design specifications:

If any of these three results meets your design specifications, you can proceed to GDSII Download and Application.

• If design specifications are not met:

You may need to make trade-offs in your specifications. Here are some suggestions:

A. Since SRF is a mandatory constraint, setting it excessively high may lead to an overemphasis on SRF and misleading the results. Keep SRF appropriately above the operating frequency.

B. The layouts generated may have varying lengths and widths. If conditions permit, you can relax the constraint on either of them to find a better solution. Note: these are optional inputs, leave these blank if no constraints required.

C. If you need an inductor with a higher Q, you should choose the thickest layer available in your technology node.

D. The generated results are the closest solutions to your input specifications. You can adjust your input for Q and L based on trade-offs if input specificationss are not all met. If RFIC-GPT does not yield results that match your requirements, please contact us: service@icprophet.com. We will offer more detailed suggestions and services.

Download the layout you want from the lower right side of the webpage.

• Check on the application of GDSII: Quick Start to GDSII Application
• If you cannot directly import the downloaded GDSII file into your design environment, please download our free-provided tool RFIC-Generator.

Note: please refer to Chapter “Draw a symbol in Virtuoso” if you have difficulty in symbol drawing.

Use the provided GDSII for electromagnetic simulation to obtain the S-parameter file.

Create a symbol and a testbench compliant with industry standards as follows:

• differential input

• single-ended input

• $L$

• $Q$

• Design Frequency (GHz)

input range: 0.5GHz ~ 85GHz

Design frequency refers to the operating frequency of the transformer in a specific circuit. For now, RFIC-GPT supports a range between 0.5GHz and 85GHz.

• Primary Coil Quality Factor Q_pri

input range: 2 ~ 50

Q_pri indicates the loss and efficiency of the primary coil at the operating frequency. The higher the Q_pri, the lower the energy loss, the higher the performance. The range of Q_pri typically falls between 2 and 50.

Tips for setting the Q: Setting the Q to around 10 suffice for most on-chip transformer scenarios. If the required Q is unclear, we suggest you to set the inductance $L$ first, then adjust the Q upwards from 10. Observe how high the Q can go while satisfying the determined $L$. Note that the technology node and layer thickness should be chosen too.

• Primary Coil Inductance L_pri (pH)

input range：40pH-6000pH (when the node is 130nm, the upper boundary is raised to 25000pH)

The inductance is measured in picohenries(pH). Choosing the correct inductance is crucial for ensuring impedance matching and efficient signal transmission. The inductance here can be regarded as a summation of both the inductive and capacitive properties of the inductor coil. For a two-port network, L_pri can be calculated as follow:

$$L\_pri=\frac{imag(Z_{11})}{\omega}, \omega=2\pi\times freq $$

• Secondary Coil Quality Factor Q_sec

input range: 2 ~ 50

Q_sec indicates the loss and efficiency of the secondary coil at the operating frequency. The higher the Q_sec, the lower the energy loss, the higher the performance. The range of Q_sec typically falls between 2 and 50.

Tips for setting the Q: Setting the Q to around 10 suffice for most on-chip transformer scenarios. If the required Q is unclear, we suggest you to set the inductance $L$ first, then adjust the Q upwards from 10. Observe how high the Q can go while satisfying the determined $L$. Note that the technology node and layer thickness should be chosen too.

• Secondary Coil Inductance L_sec (pH)

input range：40pH-6000pH (when the node is 130nm, the upper boundary is raised to 25000pH)

The inductance is measured in picohenries(pH). Choosing the correct inductance is crucial for ensuring impedance matching and efficient signal transmission. The inductance here can be regarded as a summation of both the inductive and capacitive properties of the inductor coil. For a two-port network, L_sec can be calculated as follow:

$$L\_sec=\frac{imag(Z_{22})}{\omega}, \omega=2\pi\times freq $$

• Coupling Coefficient k

input range：0 ~ 1

Coupling Coefficient k represents the degree of electromagnetic coupling between the primary and secondary coils. The closer the coupling coefficient is to 1, the tighter the coupling between the primary and secondary coils, and the higher the energy transfer efficiency. An appropriate value of k ensures efficient energy transmission in the transformer.

• Technology Node

At present, the technology nodes we support include 22nm, 28nm, 40nm, 55nm, 65nm, 110nm and 130nm.

• Primary Coil Metal Layer Thickness (µm)

You should choose the metal layer thickness in accordance with your design and the corresponding technology files.

Different metal layers have varying thicknesses and dielectric properties, and the electrical performance of coils is primarily related to the thickness of the metal layer. Please refer to the techfile or the .PROC file of the PDK and check the data.

Tips for setting the metal layer thickness: The accuracy of the results improves as the chosen metal layer thickness closely matches the thickness of the metal layer you used in your design.

• Secondary Coil Metal Layer Thickness (µm)

Please refer to the description of Primary Coil Metal Layer Thickness above.

• Transformer Type

There are currently 3 available types: Type 1 , Type 2 and Type 3 .

• Type 1 : a transformer with a phase difference of 180 degrees between the primary ports and the secondary ports;
• Type 2 : a transformer with the primary ports and the secondary ports in phase;
• Type 3 : a transformer in which the two terminals of either coil have a phase difference of 180 degrees.

Type 2 and Type 3 require the primary coil and secondary coil on the same layer. While the primary coil and secondary coil of Type 1 can be either in the same layer or in two adjacent layers.

• Signal Input Type

Choose the right Signal Input Type according to your design:

• DIFF_DIFF: The signal is differentially input into the primary coil and differentially output from the secondary coil, which is commonly used to preserve the signal's differential characteristics, help resist interference and suppress noise.
• SINGLE_DIFF: The signal is input as single-ended into the primary coil and output as differential from the secondary coil, which is commonly used for signal conversion.
• DIFF_SINGLE: The signal is input as differential into the primary coil and output as single-ended from the secondary coil, which is commonly used for signal conversion.

—-

• Max Layout Length (µm) & Max Layout Width (optional)

Max Layout Length/Width refers to the length and width constraints of the generated layout. Fill in the blanks according to your design requirements. You can also leave this blank. Generally, the larger the area, the more turns of the primary/secondary can be wound, resulting in a higher inductance value.

Fill in the “Transformer Specifications” according to your design. Click “Calculate” and you will get six sets of results and their GDSII files, each of which has a different focus point:

1. optimized towards Q_pri;
2. optimized towards L_pri;
3. optimized towards Q_sec;
4. optimized towards L_sec;
5. optimized towards k;
6. optimized towards all specifications and error-balanced.

The corresponding GDSII files are provided as well.

• If the calculated results meet design specifications:

If any of these three results meets your design specifications, you can proceed to GDSII Download and Application.

• If design specifications are not met:

You may need to make trade-offs in your specifications. Here are some suggestions:

A. If you need a secondary coil with a higher Q_sec, you should select the thickest layer available in your technology node, otherwise the result may not be satisfying. As shown in the following example, Q_sec is set as 14 and L_sec is set as 1000. The calculated result will fail to match if you set Secondary Coil Metal Layer Thickness as 0.85.

B. The layouts generated may have varying lengths and widths. If conditions permit, you can relax the constraint on either of them to find a better solution.
As shown below, when setting the specs as Q_pri=14, L_pri=1000pH, Q_sec=13, L_sec=1000pH, k=0.6, increasing the Max Lay. Width within your design constraints can achieve a solution close to your target specs.

C. When the primary and secondary coils are on the same layer, a higher Q is usually achievable. However, there will be a significant correlation between the inductances of the primary and secondary coil. If the inductances do not meet your target, please try other transformer types with the primary and secondary coil on different layers.

D. The calculated results are the closest solutions to your input specifications. You can adjust your input for Q and L based on trade-offs if input specificationss are not all met. If RFIC-GPT does not yield results that match your requirements, please contact us through the contact inormation provided below. We will offer more detailed suggestions and services.

Download the layout you want from the lower right side of the webpage.

• Check on the application of GDSII: Quick Start to GDSII Application
• If you cannot directly import the downloaded GDSII file into your design environment, please download our free-provided tool RFIC-Generator.

Note: please refer to Chapter “Draw a symbol in Virtuoso” if you have difficulty in symbol drawing.

Use the provided GDSII for electromagnetic simulation to obtain the S-parameter file.

Create a symbol and a testbench compliant with industry standards as follows:

• differential input & differential output

• single-ended input & differential output

• differential input & single-ended output

• Q_pri

• Q_sec

• L_pri

• L_sec

• k

RFIC-GPT currently offers transformer-based matching circuit design, consisting of a transformer and parallel capacitors.

• Freq. lower bound (GHz)

input range: 0.5GHz ~ 85GHz

Freq. low bound refers to the minimum operating frequency of your circuit. Note that Freq. lower bound cannot be higher than the Freq. upper bound. For single-frequency point matching network, please enter the same value for both Freq. lower bound and Freq. upper bound.

• Freq. upper bound (GHz)

input range: 0.5GHz ~ 85GHz

Freq. upper bound refers to the minimum operating frequency of your circuit. Note that Freq. lower bound cannot be higher than the Freq. upper bound. For single-frequency point matching network, please enter the same value for both Freq. lower bound and Freq. upper bound.

• Load Z (Real)

Load Z (Real) refers to the real part of the load impedance $Z_L$. Please enter the exact value at the frequency band midpoint. For example, if Freq. upper bound=25GHz and Freq. lower bound=24GHz, you should enter the real part of $Z_L$ at 24.5GHz.

The load impedance within the frequency band is equivalent to the impedance of the RC parallel circuit ($R_L || C_L$) obtained from $Z_L$ at the frequency band midpoint.

• Load Z (Imaginary)

Load Z (Imaginary) refers to the imaginary part of the load impedance $Z_L$. Please enter the exact value at the frequency band midpoint. For example, if Freq. upper bound=25GHz and Freq. lower bound=24GHz, you should enter the real part of $Z_L$ at 24.5GHz.

• Target Z (Real)

Target Z refers to the optimal load impedance that allows maximum power transfer and minimum signal reflection, also known as $Z_{opt}$. If a matching network has a low return loss, then $Z_{in}$ approximates $Z_{opt}$. In other words, when a matching network is well-designed and well-tuned to match the load impedance with the source impedance, the input impedance of the matching network closely resembles the optimal impedance for maximum power transfer or other desired performance characteristics.

Target Z (Real), or Z_opt (Real), refers to the real part of $Z_{opt}$. Please enter the exact value at the frequency band midpoint. For example, if Freq. Upper Bound=25GHz and Freq. Lower Bound=24GHz, you should enter the real part of $Z_{opt}$ at 24.5GHz.

• Target Z (Imaginary)

Target Z (Imaginary), or Z_opt (Imaginary), refers to the imaginary part of $Z_{opt}$. Please enter the exact value at the frequency band midpoint. For example, if Freq. Upper Bound=25GHz and Freq. Lower Bound=24GHz, you should enter the real part of $Z_{opt}$ at 24.5GHz.

• Maximum S11_max (dB)

Since S11 is sometimes used interchangeably with return loss and reflection coefficient Γ, we give all the definitions here to help you better understand how to set this metrics.

Return loss is a measure of the effectiveness of power transmission from a source to a load. It is defined as the ratio, usually expressed in decibels (dB), of the power reflected from the load to the power incident on the load:

$$S11=-RL=10 log⁡|P_r/P_i |=20log|V_r/V_i |=20log|Γ|=20log|(Z_{opt}-Z_{in})/(Z_{opt}+Z_{in} )|$$

As defined above, S11 is the negative return loss. RL will always be positive, and S11 will always be negative. A lower S11 value indicates a better impedance match, which corresponds to less energy being reflected and more being absorbed by the load. Therefore, we keep S11 as low as possible in RF design. S11_max is the maximum S11 that a circuit can tolerate.

• Maximum Insertion Loss IL_max (dB)

Insertion Loss refers to the loss of signal power due to the insertion of the matching network. It is defined as

$$ IL=10 log⁡(P_T/P_R) $$

where $P_T$ is the power transmitted to the load before insertion, and $P_R$ is the power received by the load after insertion. According to the diagram of matching network above, IL can also be expressed as

$$ IL=10 log⁡(Power(Port1))/(Power(Port0)) $$

The lower the IL, the better the performance. IL_max is the maximum IL that a circuit can tolerate.

• Technology Node

At present, the technology node we support include 22nm, 28nm, 40nm, 55nm, 65nm, 110nm and 130nm.

• Primary Coil Metal Layer Thickness (µm)

You should choose the metal layer thickness in accordance with your design and the corresponding technology files.

Different metal layers have varying thicknesses and dielectric properties, and the electrical performance of coils is primarily related to the thickness of the metal layer. Please refer to the techfile or the .PROC file of the PDK and check the data.

Tips for setting the metal layer thickness: The accuracy of the results improves as the chosen metal layer thickness closely matches the thickness of the metal layer you used in your design.

• Secondary Coil Metal Layer Thickness (µm)

Please refer to the description of Primary Coil Metal Layer Thickness above.

• Signal Input Type

Choose the right Signal Input Type according to your design:

• DIFF_DIFF: The signal is differentially input into the primary coil and differentially output from the secondary coil, which is commonly used to preserve the signal's differential characteristics, help resist interference and suppress noise.
• SINGLE_DIFF: The signal is input as single-ended into the primary coil and output as differential from the secondary coil, which is commonly used for signal conversion.
• DIFF_SINGLE: The signal is input as differential into the primary coil and output as single-ended from the secondary coil, which is commonly used for signal conversion.

—-

• Max Layout Length (µm) & Max Layout Width (optional)

Max Layout Length/Width refers to the length and width constraints of the generated layout. Fill in the blanks according to your design requirements. You can also leave these blank. Generally, the larger the area, the more turns of the primary/secondary can be wound, resulting in a higher inductance value.

For a matching network, S11_max and IL_max are a set of competing metrics. When setting the design specifications, you can balance the performance of the matching network by appropriately relaxing the requirement for either of these metrics. As shown in the following example, we want to match between Load Z and Target Z within 23GHz ~ 28GHz. Relaxing the requirement for S11 is conductive to achieving the target IL.

If you repeatedly submit the same set of parameters, the backend calculation may provide different results. Please choose the best one you need.

Download the layout you want from the lower right side of the webpage.

• Check on the application of GDSII: Quick Start to GDSII Application
• If you cannot directly import the downloaded GDSII file into your design environment, please download our free-provided tool RFIC-Generator.

Note: please refer to Chapter “Draw a symbol in Virtuoso” if you have difficulty in symbol drawing.

​​​​

• DIFF_DIFF

• DIFF_SINGLE

• SINGLE_DIFF

• IL example (hb simulation)

IL =-db10((pvi('hb "/net3" 0 "/PORT1/PLUS" 0'(1)) / (- pvi('hb "/net01" 0 "/PORTO/PLUS" 0 '1))))

• S11 example (sp simulation)

zm1 = zm(1 ?result "sp")
S11_zm = db20(abs(zm1 -Zopt) / abs(zm1 +Zopt))

Multi-value Matching Network allows impedance matching on multiple frequencies. On the webpage, you can directly enter a set of load impedances and optimal impedances on varying frequencies. You can also download the excel template, modify and upload.

Click on “Edit Parameters” to enter the required impedances:

In the above example, we match between $Z_L=22-24i$ and $Z_{opt}=40-5i$ on freq=24GHz; match between $Z_L=26-22i$ and $Z_{opt}=50-0i$ on freq=25GHz; match between $Z_L=28-20i$ and $Z_{opt}=60+5i$ on freq=26GHz. RFIC-GPT will calculate under your given specs and offer an optimal solution.

Multi-value matching and matching remain the same in all specs except for one unique requirement: IL fluctuation IL_fluc (dB) , input range 1 ~ 80.

IL fluctuation, or IL flatness, refers to the fluctuation amplitude of IL within the frequency band. IL_fluc can be expressed as:

$$ IL\_fluc=max(IL)-min(IL) $$

Click on “Calculate” and you will get three sets of results and their GDSII files.

Download the layout you want from the lower right side of the webpage.

• Check on the application of GDSII: Quick Start to GDSII Application
• If you cannot directly import the downloaded GDSII file into your design environment, please download our free-provided tool RFIC-Generator.

Please refer to Testbench of Matching Network.

Common types of power amplifiers include Common Source Power Amplifier(CSPA), Variable Gain Amplifier(VGA), and Cascode PA.

Please note: If the Gain can not be met even with the highest Vdd for the technology node in RFIC-GPT, please consider to design a 2-stage power amplifier and each stage can use RFIC-GPT to design.

CSPA is available on RFIC-GPT Online now. More PAs will be updated in the near future. If you cannot find the type or technology node you need, or if you require support for active circuit layouts, please email sales@icprophet.com to get offline version: RFIC-GPT Pro.

At present RFIC-GPT support CSPA at:

• Technology node: 28nm, 40nm, 65nm
• Frequency: 1~80GHz
• Supply voltage:
  1. (28nm) 0.9V, 1.0V, 1.1V
  2. (40nm) 1.0V, 1.1V, 1.2V
  3. (65nm) 1.1V, 1.2V, 1.3V
• Specs including Gain, OP1dB, AMAM, AMPM, Weights of DE_P1dB, Iq, NFmin, V_over, etc.

• M1、M3 are transistors with a default Width_per_Finger=1μm, sharing the same design parameters multipliers=Mul & Number of Fingers=NoF.
• M2、M4 are varactors with a default Width_per_Finger=1μm, sharing the same design parameters multipliers=Mul2 & Number of Fingers=NoF2.
• PortAdapter is often used in loadpull analysis, which sweeps the magnitude and phase of the load instance over a specified range, to detect potentially unstable amplifier load impedances and find an optimal value. PortAdapter properties can be set as below:

• The load impedance ZL_Real & ZL_Imag can be calculated by the design parameter ZL_Mag & ZL_Theta:

$$ Z_L = Z_0 \frac{ (1+\Gamma_r+j\Gamma_i) }{ (1-\Gamma_r-j\Gamma_i) } $$

where

$Z_0$ = 50Ω, $Γ_r$=ZL_Mag $\cdot$ cos⁡(ZL_Theta), $Γ_i$=ZL_Mag $\cdot$ sin⁡(ZL_Theta)

• Vbias: Bias voltage
• R: Compensation resistor
• Input Matching Network (IMN) / Output Mathcing Network (OMN) is replaced with an ideal balun in the schematic we provide. You can replace them with RFIC-GPT's Matching Network. Note that the load impedance will change after adding a matching network.

• Type

Please select CSPA (Common Source Power Amplifier).

• Technology Node

At present, the technology nodes we support include 40nm and 28nm. More nodes are on the way.

• Design Frequency (GHz)

input range: 1GHz ~ 80GHz

• Supply Voltage V_dd (V)

input:

(28nm) 0.9V, 1.0V, 1.1V;

(40nm) 1.0V, 1.1V, 1.2V;

(65nm) 1.1V, 1.2V, 1.3V.

• Gain lower bound (dB)

input range: 0 ~ 30

Gain is usually defined as:

$$ \text{Gain} = 10 \log_{10} \left( \frac{P_{\text{out}}}{P_{\text{in}}} \right) $$

Gain lower bound refers to the minimum requirement of gain.

• Gain upper bound (dB)

input range: 0 ~ 30

Gain upper bound refers to the upper limit of gain.

• OP1dB(dBm)≥

input range: 0 ~ 25

1dB Compression Point is defined as the point at which the linear output power and the output power of the amplifier differ by 1dB, as depicted below:

OP1dB refers to the output power at 1dB Compression Point. Please enter the minimum requirement of OP1dB.

• Weight of DE_P1dB

input range: 0 ~ 100

Drain Efficiency (DE) gets its name from FET devices, in which the primary terminal where DC power is supplied is the drain. Drain Efficiency is the ratio of output power to the input DC power:

$$ \text{DE} = \frac{P_{\text{out}}}{P_{\text{dc}}} \times 100\%$$

DE_P1dB refers to the drain efficiency at 1dB Compression Point. The higher the weight, the more RFIC-GPT will focus on DE_P1dB in the calculated results.

• Weight of Iq

input range: 0 ~ 100

Quiescent Current (Iq) here refers to the amount of current utilized by an IC when there is no external RF signal input. The higher the weight, the more RFIC-GPT will focus on Iq in the calculated results.

• Weight of NFmin

input range: 0 ~ 100

Noise Figure (NF) is the measure of signal degradation caused by the components of the system. NF can be defined as:

$$ NF = \frac{N_O^2 - N_L^2}{N_S^2} $$

$N_O$ refers to the total output noise; $N_S$ denotes the output noise introduced by the source; $N_L$ indicates the output noise due to the load.

NFmin refers to the ideal minimum NF at the Design Frequency. It is usually obtained by conducting sp simulation. The higher the weight, the more RFIC-GPT will focus on NFmin in the calculated results.

• Overvoltage V_over (V)(optional)

input range: 1.3, 1.5, 1.7, 1.9 default value: 0

Vgs_max, Vds_max or Vdg_max is the maximum amplitude of voltage across different terminals of a transistor within one period.

V*_OV_duty_cycle refers to the duty cycle of the voltage V exceeding a preset overvoltage threshold V_over within one period. Essentially, it measures the proportion of time within a cycle that the voltage Vgs, Vds and Vdg surpasses the predefined overvoltage V_over.

• AMAM / AMPM (optional)

input range: 1 ~ 20 / 1 ~ 80 default value: 2 / 10

AMAM refers to the amplitude modulation to amplitude modulation characteristic, and AMPM refers to the amplitude modulation to phase modulation characteristic. Essentially, AMAM describes how the amplitude of output changes in response to changes in the amplitude of input; AMPM indicates how the phase of output changes as the amplitude of input varies. PA distortions are amplitude dependent and phase modulated signals(having constant amplitudes) are not affected by the PA distortions. Thus, PAs are mainly characterized by their AMAM and AMPM characteristics.

• IL_in / IL_out (optional)

default value: 1dB / 1dB

ILout is the insertion loss of the matching network between your load impedance and the optimal load impedance ZL_Real and ZL_Imag, which will be provided on webpage after clicking “Calculate”. You can leave this blank and submit calculation under default value 1dB at the first time, estimate the real ILout according to the given ZL_Real & ZL_Imag, and enter the estimated ILout for a second calculation.

ILin is the insertion loss of the matching network between your source impedance and $Z_{in, conj}$. $Z_{in, conj}$ is the input impedance of PA after the output impedance matching, and will also be provide on webpage clicking “Calculate”. Same as ILout, leave this blank and submit calculation under default value 1dB at the first time, estimate the real ILin according to the given $Z_{in, conj}$, and enter the estimated ILout for a second calculation.

• Stability factor K_f & B_1f

Stability, in referring to amplifiers, refers to an amplifier's immunity to causing spurious oscillations. The oscillations can be full power, large-signal problems, or more subtle spectral problems that designers might not notice. K_f and B_1f are two important stability factors that can be obtained by S parameters:

$$ K_f = \frac{1 - |S_{11}|^2 - |S_{22}|^2 + |\Delta|^2}{2 |S_{12}| |S_{21}|} > 1 $$

$$ |\Delta| = |S_{11} S_{22} - S_{12} S_{21}| $$

$$ B_{1f} = 1 + |S_{11}|^2 - |S_{22}|^2 - |\Delta|^2 > 0 $$

• Under fixed Gain and OP1dB, you can optimize the active circuit toward DE_P1dB, Iq or NFmin by adjusting their weights. For example, under the following specifications, RFIC-GPT gives a result with an Iq = 14.07mA. If you need a smaller Iq, increase Weight of Iq from 8 to 80, and re-calculate. Iq is consequently reduced from 14.07mA to 10.9mA.

• With the $ZL\_Real$ and $ZL\_Imag$ given in the table Generated Power Amplifier's Specifications (including the recommended load), you can generate an output matching network with RFIC-GPT's Matching module;
• With the $Z_{in,conj}\_Real$ and $Z_{in,conj}\_Imag$ given in the table Generated Power Amplifier's Specifications (including the recommended load), you can generate an input matching network with RFIC-GPT's Matching module.
• Note that if your input specifications are not set properly, the calculated results will be NULL. Check if Gain lower bound is higher than Gain upper bound, or OP1dB may be set too high, etc. Reset the specifications and re-calculate.—-

If the generated PA's specifications meet your requirements, click “Display design parameters”. Both design parameters and generation code will be shown.

You can enter the generation code in our free-provided tool RFIC-Generator, which will generate schematic, testbench and simulation files for you. You can conduct simulations in your own design environment to verify the results RFIC-GPT provided on the webpage.

Click “RFIC-Generator” button and install following RFIC-Generator User Guide. It instantly generates schematic, testbench and simulation files in your design environment. You can conduct simulations yourself to verify the results.

GDSII files from RFIC-GPT can be easily applied in standard design platforms including but not limited to Cadence Virtuoso, Keysight ADS, Siemens(Mentor) L-Edit, Synopsys CC, Laker, LayoutEditor, etc.

The results can be downloaded and applied in standard design platforms such as Cadence Virtuoso, Keysight ADS, etc. Below is an example using Cadence Virtuoso to illustrate how to apply the downloaded GDSII file to your design.

Download GDSII

Click “Download GDS layout” and you will get a zip file. The zip includes:

• .gds, the GDSII file;
• .txt, the generation code only required by RFIC-Generator.

Import GDSII

In Virtuoso CIW menu, click file-import-stream to import the GDSII file:

• Enter the path to the GDSII file in Stream File;
• Choose your target library name in Library;
• Choose the technology node which your target library is attached to in Attach Tech Library;
• Click Translate or Apply.

Modify Metal Layers

• If you need more metal layers information, please visit chapter “Stream and Datatype of metal layers in PDK”.
• Different PDKs or different Metal Stacks have different names for metal layers. To ensure the applicability of the generated PAs offered by RFIC-GPT, the provided GDSII files uniformly use the names M1, M2 and M3 for the metal layers involved. M3 stands for the top layer, and M1 stands for the bottom layer.
• After importing the GDSII file into your environment, you should change the current metal layer to the exact metal layer used in your design, such as M7, M8 and AP. Please refer to our guide below and modify the layers carefully, or there will be fake design rule violations.

Open the imported layout, check Used in the left-side Layers panel, and you will see the metal layers used by the device.

• In the Layers panel, select the metal layer you want to modify, then click on V (Visibility). This is to hide all other layers, making it easier for you to make a global selection on the layer.
• Next, press Ctrl+A to select all the shapes in the layout. Press Q to open the Edit Properties window. Press Ctrl+A again to select all the shapes displayed on the left. Then in the right Attribute panel, change the Layer to your target layer (e.g. from M3 drawing to AP drawing). Finally click on apply to apply the modification.

• Repeat the steps above to replace the original M1, M2 and M3 layers with the three metal layers you need (typically the top three layers). Finally the modified result should look like this (e.g. `M3` to `AP`, `M2` to `M8`, and `VIA3` to `RV`):

Modify VIAs

If you need to adjust VIAs in the layout, delete the current VIAs and then press O to perform autovia in the respective area.

Modify PINs

If the current PINs cannot be recognized in your design environment, or they are not displayed correctly, you need to manually add them. Select Create→Pin in the menu:

Select the corresponding metal layer of the PIN in the left Layers panel, type in the PIN names (e.g. lp\lm for an inductor), and draw a rectangle on the layout to cover the original PIN.

RFIC-Generator is a tool for generating RFIC chips. As a module currently integrated in the Cadence Virtuoso, it can rapidly generate GDSII layouts of various inductors and transformers based on geometric parameters provided by designers. These layouts can be directly used for electromagnetic simulation without the tedious iterations of manual layout editing, and these layouts can be adjusted for simulation.

Comparing to RFIC-GPT, RFIC-Generator doesn’t have AI algorithm so its result can’t guarantee accuracy. But, RFIC-Generator also serves as an auxiliary tool of RFIC-GPT Online service. With the ‘generation code’ calculated by RFIC-GPT, RFIC-Generator can autonomously generate DRC-clean passive devices and active circuits with accuracy.

Click here to download RFIC-Generator

When RFIC-Generator is being installed, it will use the below files of Virtuoso environment. Here are their functions and description.

The cds.lib file is an ASCII file used to define libraries. The file maps user library names to physical directory paths. Applications read the cds.lib file to identify the libraries they can use. Virtuoso provides a default cds.lib file in the directory your_install_dir/share/cdssetup. You can create a new cds.lib file in a different path (like /home/) and use the command: SOFTINCLUDE your_install_dir/share/cdssetup/cds.lib to link it to the default cds.lib file. During the installation of RFIC-Generator, you must have an editable cds.lib file. If you do not have permission to edit the current cds.lib file, you can create a new one and link it to the existing file.

.cdsinit file defines the startup environment of Virtuoso. In this file, you can write commands and custom SKILL programs which are automatically executed during Virtuoso startup. There is a default .cdsinit file in the Virtuoso software, located in the directory your_install_dir/tools/dfII/local/. (Note: The.cdsinit file is a hidden file, and you need to press Ctrl+H in Linux to display it.) To install RFIC-Generator successfully, you need an editable .cdsinit file, which can be in either the default directory or the Virtuoso startup directory. Usually, system administrators do not allow ordinary users to have edit permissions for the default directory, so you must ensure that the .cdsinit file in the Virtuoso startup directory is editable; if this file does not exist in the startup directory, you need to create one.

Note: Since only administrators can modify the read path, order, and permissions of these files, it is best to consult with the system administrator first.

You can place the downloaded installation package in any location and unzip it. However, after the installation is completed, you must not change its location, otherwise the environment variables may not work.

Cadence Virtuoso environment configuration for individuals and corporations can vary significantly. Depending on whether you are an individual user or a industrial user, we provide two installation processes for you to choose from, Script Installation and Customized Installation.

Run the install.sh in RFIC-Generator.

Step 1: Enter your path to cds.lib.

Please note:

• The cds.lib you provide must exist.
• Make sure you have read and write permissions on this cds.lib.

Step 2: Enter your path to .cdsinit.

Please note:

• Make sure your path to .cdsinit is correct;
• .cdsinit is a hidden file in Linux so please check carefully;
• We can create a .cdsinit for you if the path does not exist. Make sure you have enough permissions under the path.

If you are the adminstrator of design environment, you need input the path of .cdsinit under cadence installation directory (the default path is /tools/IC*/tools/dfII/local/.cdsinit). If local directory doesn't exsit under cadence installation directory, please create it. Then create .cdsinit file, input the below codes in this new .cdsinit file :

if（isFile（“./.cdsinit”） then loadi(“./.cdsinit”)
else if（isFile（“~/.cdsinit”） then loadi(“~/.cdsinit”)))

Step 3: Set RFIC-Generator as a startup item in Cadence Virtuoso.

• Enter y or yes, then RFIC-Generator will be loaded automatically when starting Cadence Virtuoso. You can see it in CIW menu.
• Enter n or no, then you will have to load it manually everytime. Enter load(strcat(RFIC_Generator_PATH “/Start.il”)) in CIW and press Enter.

Different from Script Installation, you have to modify cds.lib and .cdsinit manually in Customized Installation.

Step 1: Modify .cdsinit.

Since .cdsinit is a hidden file in Linux, you may have to press Ctrl+H to display it. If you cannot find .cdsinit in your Virtuoso startup path, you can create a new .cdsinit:

touch ./.cdsinit

If you are the administrator, you can modify the master .cdsinit file in your Cadence intallation path. Normally the path is /tools/IC618/tools/dfII/local/.cdsinit.

Add the following code in .cdsinit (“XX” is the location of your unzipped RFIC_Generator installation package):

RFIC_Generator_PATH="XX/RFIC_Generator"
ciwMenuInit()
load(strcat(RFIC_Generator_PATH "/Start.il"))

If the below codes are not existed in the master .cdsinit file, please add at the end if this file:

if（isFile（“./.cdsinit”） then loadi(“./.cdsinit”)
else if（isFile（“~/.cdsinit”） then loadi(“~/.cdsinit”)))

Step 2: Modify cds.lib.

cds.lib is usually in your Virtuoso startup path. If you are the administrator, you can modify the master cds.lib file in your Cadence installation path. Normally the path is /tools/IC618/share/cdssetup/cds.lib.

Add the following code in cds.lib:

DEFINE EmptyBox XX/RFIC_Generator/RFIC_Active_Generator/EmptyBox

This chapter is for Passive Generator of RFIC-Generator. You can skip this chapter if you only need Active Generator.

After your installation is completed, find layertrans.csv in your unzipped RFIC-Generator installation package:

.../RFIC_Generator/RFIC_Passive_Generator/layertrans.csv

layertrans.csv contains the following contents:

M3, M2 and M1 respectively represent the top three metal layers in your technology node. Specifically, M3 is the topmost layer, M2 is the second top layer, and M1 is the third top layer.

Check the .layermap file in your PDK and:

• find the stream number and datatype of the topmost layer(e.g. “AP1 drawing”), enter into M3_drawing_stream and M3_drawing_datatype;
• find the stream number and datatype of the second top layer(e.g. “M8 drawing”), enter into M2_drawing_stream and M2_drawing_datatype;
• find the stream number and datatype of the third top layer(e.g. “M7 drawing”), enter into M1_drawing_stream and M1_drawing_datatype;

In a similar way, VIA1 is between M1 and M2, VIA2 is betwee M2 and M3. Find the stream number and datatype of corresponding VIAs in .layermap and enter into VIAx_drawing_stream and VIAx_drawing_datatype.

Finally, enter the actual names of the top three metal layers in M1_name, M2_name and M3_name.

If you use multiple technology nodes, you should create a layertrans.csv for each node. In fact, feel free to rename and relocate the layertrans.csv according to your preferences. You only have to select the right path in the setup section.

If you need more metal layers information, please visit chapter "Stream and Datatype of metal layers in PDK".

Run the uninstall.sh in RFIC-Generator. Remember to uninstall RFIC-Generator everytime before you install a new version.

Click RFIC-Generator → Passive Generator in CIW:

RFIC Passive Generator includes three modules:

• Inductor: Input geometric parameters, output an inductor layout
• Transformer ：Input Transformer types and geometric parameters, output a transformer layout
• RFIC-GPT Code ：Input generation code from RFIC-GPT, output an inductor or transformer layout

The free-provided RFIC-Generator is not customized for various technology nodes. Therefore, layouts generated by Inductor and Transformer modules may have DRC problems, as they only listen to your input geometric parameters. However, layouts generated by RFIC-GPT Code are calculated results from RFIC-GPT. They will be DRC-clean.

Step 1: Set the path for layertrans.csv in the setup section.

We provide a template layertrans.csv in the installation package. You can load the template after you finished installation to see if RFIC-Generator is installed properly. For further usage on different technology nodes, please refer to the setup chapter.

Step 2: Enter geometric parameters.

Geometric parameters include the metal layer, number of turns, radius, width, etc. Click on the Guide button in the Geometric parameters section to check the diagram and the definitions of each parameter.

• As mentioned above, M3, M2 and M1respectively represent the top three metal layers in your technology node. Therefore, for example, if you want to use the topmost layer, you should choose M3 in this section, and modify the layertrans.csv properly.
• You can also customize the inductor's terminal length, terminal space and label in the terminal/label section. When terminal length / terminal space = -1, RFIC-Generator will autonomously determine the length and spacing appropriately.

Step 3: Enter target library and cell name.

In the Apply section, fill in Library and cell name for the generated layout. After clicking Apply, the layout will be successfully placed in that cell.

Step 1: Set the path for layertrans.csv in the setup section.

We provide a template layertrans.csv in the installation package. You can load the template after you finished installation to see if RFIC-Generator is installed properly. For further usage on different technology nodes, please refer to the setup chapter.

Step 2: Enter Transformer Type.

In the Type setting section, you should provide the layers you use in the transformer, and the Transformer Type.
Layer_pri is the primary coil layer, and Layer_sec is the secondary coil layer. M3, M2 and M1 respectively represent the top three metal layers in your technology node. Specifically, M3 is the topmost layer, M2 is the second top layer, and M1 is the third top layer. You should specify their target layers in Step 1.

Transformer Type is closely related to the metal layers you have selected.

• If the primary and secondary coils are on the same layer (Layer_pri =Layer_sec), you will have five options for Transformer Type:
  • Parallel-Parallel
  • Serial-Serial
  • Serial-Parallel
  • In/Out sameside
  • Overlapping inductor type * If the primary and secondary coils are on different layers(Layer_pri≠=Layer_sec), you will have two options for Transformer Type:
  • Non-coaxial
  • Coaxial

Click on the Guide button in the Type setting section to check the diagram and the definitions of each types and their parameters.

Step 3: Enter geometric parameters.

• Every Transformer Type has different Geometric parameters.
• You must select a Transformer Type before you fill in Geometric parameters.
• Each time you select a Transformer Type, the Geometric parameters section will automatically refresh.
• Before you select any Transformer Type, the default Transformer Type displayed does not correspond to the default Geometric parameters. Clicking the Apply button will cause error.

Please strictly follow the above to make sure your transformer layout is generated smoothly.

• You can also customize terminal length, terminal space and label of both primary and secondary coils in the terminal/label section. When terminal length / terminal space = -1, RFIC-Generator will autonomously determine the length and spacing appropriately.

Step 4: Enter target library and cell name.

In the Apply section, fill in Library and cell name for the generated layout. After clicking Apply, the layout will be successfully placed in that cell.

RFIC-GPT Code serves as an auxiliary tool of our online service RFIC-GPT. Within seconds, you can get a DRC-clean passive device layout, whose performance perfectly meets your specifications.

Step 1: Set the path for layertrans.csv in the setup section, and click Load.

We provide a template layertrans.csv in the installation package. You can load the template after you finished installation to see if RFIC-Generator is installed properly. For further usage on different technology nodes, please refer to the setup chapter.

You may have noticed that there is an extra section Layermap transform. Your layertrans.csv will be parsed and import into this section after clicking Load.

Step 2: Enter generation code in the RFIC Generation Code section.

After submitting calculation on webpage, within seconds a few sets of calculated results will be displayed. Click Download GDS layout on your most satisfying result and you will get a zip package consisting of a .txt file and a .gds file. In the .txt is the generation code for your calculated result:

Enter the string into the RFIC Generation Code section:

Step 3: Customize your terminal.

You can customize terminal length, terminal space and label in the Terminal section.

• For transformers, you can customize both primary and secondary coils.
• For inductors, since their is only one coil, you only have to modify terminal length(pri) and terminal space(pri).

Step 4: Enter target libray and cell name.

In the Apply section, fill in Library and cell name for the generated layout. After clicking Apply, the layout will be successfully placed in that cell.

Step 5: Use the inductor or transformer module for fine-tuning after generating layouts with RFIC-GPT Code.

After clicking Apply, not only the layout will be generated, but the geometric parameters of the layout will also be updated into the inductor or transformer module. You can fine-tune the geometric parameters according to your needs.

Errors and solutions:

No such file means your path for layertrans.csv is wrong. Check the path and try again.

Incorrect format filling in 'web output' means your generation code is wrong. Check the string and try again.

The 'Layermap transform' module was incorrectly filled means the format your input data in the Layermap transform section is wrong. target stream and target datatype should all be integers, and Mx_name should be set properly according to your PDK. Check the data and try again.

Step 1: Import a default library.

First in the “RFIC path” section, select your path to your installation package. Choose the active circuit pattern (only CSPA for now), click Load and a default library will be added to your design environment. The default library contains 4 cells: DM_lvt4t, DM_lvt6t, lvt4t and lvt6t. Note that 4t transistors and 6t transistors have different terminals, thus requiring different wiring. Therefore, we put them in two cells. DM cells are used to measure stability, where the portAdapter are absent. Everytime you click Load, a new default library will be imported and your original one will be overwritten. Make a backup if you need before every Load.

Step 2: Replace default instances in the default library.

As mentioned above, the default library added in Step 1 has different cells with different instances and wiring. You can replace the default 4t or 6t transistors with real 4t or 6t transistors in your PDK. Specify your transistors in the Instance to replace section.

For example, if you want to use a 6t transistor like nmos_rf_lvt_6t, you should choose the 6t cell like CSPA_lvt6t in the Source Schematic section, as the wiring differs between 4t and 6t schematics. Otherwise the files may end up broken. If, unfortunately, you accidentally mis-replaced 4t cells with 6t, you should repeat Step 1. The new default library will overwrite the broken old one.

Step 3: Select path to the Model Library in your PDK.

Select path to your model file in the “model Path” section. For reference only, it is usually called toplevel.scs located in the “models” folder.

Step 4: Enter generation code

Check the generation code from RFIC-GPT and enter into the “generation code” section above. Click “Apply”.

Step 5: Open webdisplay_state1 and verify the results.

Here we use transformer as example. Inductor modification is the almost the same.

Step 1: Input the “generation code” which you get in RFIC-GPT website, then layout is generated.

Step 2: Click the “Transfermer” Section as below picture, the related parameters will be directly listed. Please note: you can click “Guide” Button for detail parameters explanation.

Step 3: Layertrans file chosen in Setup File should match the corresponding PDK you are designing. Otherwise, some or all metal layers will be lost. (Information to fill the layertrans file can be found: “Stream and Datatype of metal layers in PDK”.

Open the new created Cell, you can get the modifed layout:

Q: How to apply the calculated results from RFIC-GPT in a closed design environment?

A: Please try the below methods:

• Download our free tool RFIC-Generator and install it in your closed environment, once and for all. Feed RFIC-Generator with the generation code provided by RFIC-GPT, and the corresponding layout will be generated for you immediately. Please refer to our RFIC-Generator User Guide, or email to service@icprophet.com for support.
• We have offline version: RFIC-GPT Professional, which is more powerful than online version and pay to use. Please email to sales@icprophet.com for evaluation or quotation.

Q: I use mobile to access RFIC-GPT Online, but it can't display in full width, how to solve it?

A: Just try Firefox, Chrome or other mobile browser, using landscape mode , you can have a wider display which is enough.

Q: Which specific technology node is supported?

A: The properties of top-layer passive devices are mainly related to the metal layer thickness and material properties. Check your PDK files for the thickness of the layer you are using, and select the metal layer thickness on our website RFIC-GPT. The closer the selected metal layer thickness is to the actual layer thickness you are using, the more accurate the results will be. Active circuits' calculated results can be verified under mainstream processes. If you need more support, please contact us via email.

Q: Why is the metal layer missing in the downloaded layout?

A: If you cannot see the metal layers after opening GDSII file with Cadence Virtuoso, please check the Metal Layer Thickness you input on the webpage first. The Metal Layer Thickness you select should match the thickness of the layer you use in your node. Check the layer thickness in your PDK file and try again. If the Metal Layer Thickness differs significantly from the actual layer thickness in your attached PDK, the metal layer will not be displayed. This is to avoid using RFIC-GPT layouts as actual layouts when there is a mismatch in technology nodes.

If you intentionally set different metal layer thicknesses for research or other purposes, please unbind the PDK associated with your current project. The metal layers will be displayed correctly.

Q: Are the calculation results from RFIC-GPT always under 85°C?

A: Yes. 85°C is a more applicable and stringent condition because of the overheating in real chips. Many commercial products requires a 85°C simulation test. Quality factor Q is significantly influenced by temperature, while other specifications are less affected. For reference only, compared with 85°C, Q increases approximately by 2 under 27°C. If you need precise results under other temperatures, please email sales@icprophet.com to get RFIC-GPT Pro.

Q: The calculated results from RFIC-GPT cannot reach the design specifications I entered. How should I improve the performance?

A: The reason for this situation may be unreasonable specification settings. Please strike a balance between each specification, subtly lower the unattainable ones or increase those with significant margin, and re-calculate. Alternatively, consider trying a different metal layer thickness. You can also refer to: Inductor trade-off, Transformer trade-off, Matching trade-off. If the calculated results still do not meet your specifications, please email to service@icprophet.com for support.

Q: How to raise Q_pri & Q_sec without modifying inductances and coupling coefficient k?

A: It may be necessary to use stacked metals as coils, but only a few transformer types can be achieved with stacked metals. Stacked metals are not applicable in complex structures.

Q: Are there other structures for inductors / transformers?

A: We are working on new structures of both inductors and transformers. If the provided result or the current structures cannot reach your specifications perfectly, you can download the GDSII file and make slight modifications to them, such as the width, radius, and space. In most cases, it should help meeet your requirements. If you have suggestions, please feel free to email service@icprophet.com。

Q: Can RFIC-GPT provide transformers with taps?

A: Only offline version RFIC-GPT Pro provides this function, but it's pay to use. Please email sales@icprophet.com for evaluation or quotation.

Q: Does RFIC-GPT support GaN, GaAs or substrate?

A: Currently RFIC-GPT Online version only offers design for CMOS technology. GaN, GaAs and substrate passive devices/circuits are in our future update plan. Please stay tuned for upcoming releases.

Q: Can I cite RFIC-GPT in my paper?

A: Of course, you can cite RFIC-GPT in your papers or articles.

Q: For downloaded transformer layouts and their primary & secondary coils, which one is the top metal layer, and which one is the second top layer?

A：Please refer to Quick Start to GDSII Application.

Q: During RFIC-Generator installation, 'Permission denied' is displayed, how to solve it?

A: Please make sure you have enough permissions on cds.lib,.cdsinit and the corresponding paths. You can use the below “chmod” commands to add permissions:

chmod +rw .cdsinit \
chmod +rw cds.lib

Then re-run 'install.sh'.

If you install RFIC-Generator in vmware, don’t put RFIC-Generator directory under /mnt/hgfs of vmware tools, which is a shared directory. It may crash.

If you are personal user, you can put it under /home.

If you use Virtuoso from /home directory, please put cds.lib and .cdsinit files under your own ‘home’ directory. Then “Permission Denied” error will not happen.

When Virtuoso starts, it will load .cdsinit file from starting directory. Non-admin user usually need not modify the general .cdsinit file. Instead, modify private.cdsinit under the starting directory.

If there is no.cdsinit file under /home, you can input/home/IC/.cdsinit during the installation of RFIC-Generator and this file can be automatically created.

Q: After installing RFIC-Generator, when using the Passive Generator, an error occurs: “Error gets: argument #1 should be an I/O port (type template = “p”) - nil” (also see the below pic), or there are issues such as “Permission Denied” and etc., that make it unusable. What is the reason?

A: Please extract the downloaded RFIC-Generator package on a Linux system before installing. Extracting on Windows system and installing on a Linux system will result in various errors.
If you have already extracted it on a Windows system, please uninstall the RFIC-Generator and reinstall it according to the requirements.

Q: Is RFIC-Generator only usable in Cadence Virtuoso IC618? Is it compatible with IC51?

A: RFIC-Generator is compatible with IC618 and we cannot guarantee the compatibility with other versions. We can provide a customized compatible version of RFIC-Generator for a fee, if needed. Please email sales@icprophet.com for further assistance.

Q: Can you provide RFIC-Generator on ADS?

A: RFIC-Generator on ADS is available with additional payments. Please email sales@icprophet.com for inquires.

Q: Which EM tool shall I use to simulate the layouts or schematics downloaded from RFIC-GPT?

A: Any standard EM simulation tool can be used. If you are using EMX, please add some commands in EMX setup window (noted in the next question). There is no specific setup rule needed for other EM Simulation Tools.

Q: How to verify the performance results of a passive network?

A: Recommended procedure: After downloading the GDSII from RFIC-GPT, import it into Virtuoso. Then create a symbol, and place the symbol in the corresponding testbench for inductors, transformers, or matching circuits. After inserting the provided formulas in ADE L, you can obtain the simulation results for the passive network. Refer to: Draw a symbol, Testbench for Inductors, Formulas for Q and L of inductors.

Q: Why do the results of my EM simulation differ from what I get from RFIC-GPT Online?

A: Suppose you are using EMX, please make sure you are also applying the same setup rules:
1. In the EMX setup window, click “Advanced Option”. In the “Other command-line options”, enter the following command in the EMX (or EMX_DATA) column:

--temperature=85 --uniform-sources

2. Prefereably choose n-port in EMX for any device you downloaded from RFIC-GPT Online.

After this, please retry the simulation. If the results still differ >5% than the data provided on RFIC-GPT website, please email service@icprophet.com.

Q: Why can't EMX simulation be used after renaming layouts or schematics generated by RFIC-GPT?

A: The issue arises because the new name includes “.” character, which violates EMX naming rules, preventing EMX from functioning properly. Here's how to solve it:

• If you import the layout or schematic directly into Virtuoso after downloading from RFIC-GPT, avoid using “.” in the new name.
• If you download the code from RFIC-GPT and then use RFIC-Generator to produce the corresponding layout or schematic, rename it in the “Cell name” field at the bottom right of the RFIC-Generator interface, ensuring the new name does not include a “.” character. As below picture shows:

RFIC-GPT Professional version (RFIC-GPT Pro) is an offline software and provided to commercial company users. It is install in designer’s environment, embedded tightly in layout tool. Professional version can be used more convenient than online version, supports more device and circuit structures, generates and adjusts GDSII more easily w/ functions such as Dummy fill, Guard-ring etc.

The difference among RFIC-Generator, RFIC-GPT Online and RFIC-GPT Pro is as follows:

If you have interesting to eval or buy RFIC-GPT Pro, pls email sales@icprophet.com

If your questions or problems are not included, please email service@icprophet.com.

In Testbench, it is often necessary to generate symbols for the required devices. This section takes drawing an inductor’ symbol as an example to introduce how to operate in Virtuoso.

1.Create Cellview

2.Choose analogLib in the Library column and n-port in the Cell column

3.Enter number in the Number of ports column and paste the S-parameter path in the S-parameter data file column

Tip:
For inductors without Center Tap, fill “2” in the Number of ports column.
For inductors with Center Tap, fill “3” in the Number of ports column.
For transformers without Center Tap, fill “4” in the Number of ports column.
For transformers with Center Tap, fill “6” in the Number of ports column.

4.Use Create → Pin to creat pins

5.Use Create → Cellview → Form_Cellview to create symbol

6.Enter the position that you wish your pins to be in and click OK

7.Symbol creation completed

This section introduces how to find the “drawing_stream” and “drawing_datetype” of the top three metal layers.

Firstly, open the “techfile” file in your PDK folder. Search for (Ctrl+F) “layerrules” in order to understand the corresponding layer rules of your PDK. Generally speaking, the last metal layer information in your techfile is the topmost layer in the physical manufacturing process.

Demonstration:

In this instance, ALPA/MTT2/TM1 (metal layers) and PA/TV2 (cut layers) are the information we need. After this, search for (Ctrl+F) the names ALPA/MTT2/TM1/ PA/TV2 with drawings after them in the “layermap” file. The numbers after drawing are the drawing_stream and drawing_datetype respectively.

The above is only for demonstration, please refer to your own PDK in search of the infomation needed.

v1.240520 Hotfix 1

• bug fixed

v1.240520

• More Transformer architectures provided
• Algorithms updated

v1.240125

• The first release of RFIC-GPT in English

v1.240520 Hotfix 1

• Synchronize updates with RFIC-GPT v1.240520 Hotfix 1
• bug fixed

v1.240520

• Synchronize updates with RFIC-GPT v1.240520
• More Transformer architectures provided
• Fix bugs

v1.240125

• For RFIC-GPT v1.240125